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DE1 User Manual
2.2 Block Diagram of the DE1 Board
Figure 2.2 gives the block diagram of the DE1 board. To provide maximum flexibility for the user,
all connections are made through the Cyclone II FPGA device. Thus, the user can configure the
FPGA to implement any system design.
Figure 2.2. Block diagram of the DE1 board.
Following is more detailed information about the blocks in Figure 2.2:
Cyclone II 2C20 FPGA
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18,752 LEs
52 M4K RAM blocks
240K total RAM bits
26 embedded multipliers
4 PLLs
315 user I/O pins
FineLine BGA 484-pin package
Serial Configuration device and USB Blaster circuit
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Altera’s EPCS4 Serial Configuration device
On-board USB Blaster for programming and user API control
JTAG and AS programming modes are supported
SRAM
6
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